Logic Analyzer 235MHz State, 136 Channels,
2GHz Timing, 125ps MagniVu Acquisition, 512Kb Memory Dept
The TLA5204 is a logic analyzer with a bandwidth of 235 MHz state and 136 channels. Designed to help you to verify and debug hardware designs, processor and bus designs and embedded software and hardware intergration.
Stand alone system
34/68/102/136 channel configuration (This unit has 136 channels)
Memory dept per channel: 512 kb
Timing record length: 500 ps (2 GHz)/ 32 Mb to capture intermittent events over a wide time window
125 ps resoultion MagniVu acquisition simultaneous with timing or state acquisition, to find elusive problems
Glitch and set up/hold violation triggering and display, to find and display elusive hardware problems
235 MHz state acquisition provides analysis of high-speed synchronous digital circuits
Time-correlated digital analog view (iview) to clearly see analog anomalies affecting digital signals
Internal display size: 10.4 inch (26,4 cm)
Resolution: 1024 x 768
Number of ext. displays: 2
Ext. display resolution: 1024 x 768 (primary), 1600 x 1200 (secondary)
Standard data window types: waveform, listing, graph, histrogram (performance analysis), source code, protocol
Operating system: Microsoft Windows XP Professional with multi-language user interface
Remote control with Microsoft.NET
Microsoft XP Professional PC controller/ user interface / network connectivity
LAN port type: 10/100BaseT
USB port: four USB 2.0
Dimension (HxWxD): 11.2 x 17.5 x 11.35 in.
Weight net without probes: 26 lb
Measurement functions:
Timing and state analysis
Single-processor/bus analysis
Real-time instruction trace analysis
Protocol analysis
Source code debug
Performance analysis
Digital signal quality analysis
€ 5,500 (net) $6,930 (US)